1. Field of the Invention:
The present invention relates to a method of manufacturing a compound semiconductor wafer for use in an electronic device, and more particularly to a method of manufacturing a compound semiconductor wafer having a GaAs epitaxial layer of high resistivity.
2. Description of the Related Art:
GaAs wafers are used in electronic devices, e.g., OEICs, HEMTs, and ion-implanted FETs.
Electronic devices having a GaAs wafer fabricated from a bulk crystal have device characteristics, for example, hysteresis of current vs. voltage characteristics, a frequency-depending dispersion of drain conductances, and a kink effect, for a GaAs field-effect transistor (FET). It has been believed that these device characteristics may be deteriorated by impurities and defects which are present in the crystal.
In order to avoid such deteriorations of the device characteristics, there has been proposed an electronic device wafer having a barrier layer which comprises an epitaxial layer that is of higher quality than bulk crystals. Some of such wafers that are already used in electronic devices have a superlattice epitaxial layer of AlGaAs/GaAS produced by the MBE process or have an undoped epitaxial layer of GaAs formed by the halide process.
In semiconductor devices composed of compound semiconductors belonging to Group III-V of the periodic table, a buffer layer is employed to insulate an operative layer (active layer) from the wafer or to separate devices from each other in an integrated circuit. It is of great importance for improved device characteristics that such a buffer layer have a high resistance, i.e., being semi-insulating.
Conventionally, high-resistance layers in semiconductor devices composed of compound semiconductors belonging to Group III-V have generally been fabricated by the vapor-phase epitaxial growth process. Such high-resistance layers may be rendered semi-insulating by either supplying a doping gas containing an impurity for semi-insulation through a bypass pipe during vapor-phase epitaxial growth or adding a deep level impurity to a source material used in the vapor-phase epitaxial process and then doping an epitaxial layer on the surface of the wafer with the deep level impurity during vapor-phase epitaxial growth.
According to the former process, however, the compound of the deep level impurity introduced through the bypass pipe tends to be decomposed and deposited in the bypass pipe, or the deep level impurity is liable to react with hydrogen chloride (HCl) in the bypass pipe, resulting in the formation of a chloride that is delivered through the bypass pipe. Therefore, if the amount of such a deep level impurity to be doped is increased, then the concentration of hydrogen chloride is increased, thus undesirably etching the wafer.
The latter method is disadvantageous in that if the equilibrium segregation coefficient of the source of deep level impurity with respect to the source material is small, then a required amount of deep level impurity cannot be supplied.
The source of deep level impurity may be iron, chromium, vanadium or the like, which is a so-called "deep acceptor impurity". The device characteristics are deteriorated when the deep acceptor impurity enters from the buffer layer into the active layer. Furthermore, if an FET is fabricated by using a semiconductor wafer in which a layer with a deep acceptor impurity contained therein is formed in the interface between a buffer layer and an active layer, then a deep trap layer is created in the interface between the buffer layer and the active layer. Since such a deep trap layer traps electrons flowing through the active layer and discharges electrons into the active layer, it is responsible for causing noises.
Whereas in the case when an impurity which forms a shallow level can be compensated by another impurity which forms an opposite conductivity type shallow level, there is no adverse effect, the introduction of an impurity which forms a deep level essentially has an adverse effect on the crystal.
The applicant has previously developed a process of manufacturing a semi-insulating compound semiconductor substrate in which a p-type epitaxial layer formed on a compound semiconductor wafer is rendered semi-insulating by annealing. The manufacturing process is disclosed in Japanese laid-open patent publication No. 4-98000.
However, subsequent research has revealed that while the disclosed manufacturing process is effective to make the epitaxial layer semi-insulating, it is unable to avoid a side gate effect in an integrated circuit environment, that is, the defect of drain current fluctuations that are caused by the voltage of an adjacent device.